Semiconductor Devices Research Laboratory

Papers in International Referred Journal


  1. "Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications", Rakhi Narang, Manoj Saxena, R.S. Gupta, and Mridula Gupta, (Accepted For Publication Sept. 2012). Journal of Semiconductor Technology and Science

  2. "Numerical analysis of localised charges impact on Static and Dynamic Performance of Nanoscale Cylindrical Surrounding Gate MOSFET Based CMOS Inverter", Rajni Gautam, Manoj Saxena, R.S.Gupta , and Mridula Gupta, Microelectronics Reliability, (in press), 2012.

  3. "Numerical Model of Gate All Around MOSFET With Vacuum Gate Dielectric For Biomolecule Detection", Rajni Gautam, Manoj Saxena, R.S.Gupta, and Mridula Gupta, IEEE Electron Device Letters, vol.33, in press, 2012.

  4. "An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design" Pujarini Ghosh, Subhasis Haldar, R.S.Gupta and Mridula Gupta. (Accepted For Publication). in IEEE Transactions on Electron Devices

  5. "Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET" Pujarini Ghosh, Subhasis Haldar, R.S.Gupta and Mridula Gupta. (Accepted For Publication). Journal of Semiconductor Technology and Science

  6. "An Accurate Small Signal Modeling of Cylindrical/Surrounded Gate MOSFET for High Frequency Applications" Pujarini Ghosh, Subhasis Haldar, R.S.Gupta and Mridula Gupta. (Accepted For Publication). Journal of Semiconductor Technology and Science

  7. "A Dielectric Modulated Tunnel FET based Biosensor for Label Free Detection: Analytical Modeling Study and Sensitivity Analysis." Rakhi Narang, Reddy K. V. S., Manoj Saxena, R.S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, vol. 59, no. 10, pp. 2809-2817, Oct 2012.

  8. "Two dimensional analytical drain current model for Double Gate MOSFET incorporating Dielectric Pocket (DP-DG)" Vandana Kumari, Manoj Saxena, R.S. Gupta, and Mridula Gupta,. IEEE Transactions On Electron Device, vol 59, no. 10, pp. 2567 - 2574, 2012.

  9. "Analytical Model for Double-Gate Tunneling Field-Effect Transistor (DG-TFET) using carrier concentration approach" Rakhi Narang, Manoj Saxena, R.S. Gupta, and Mridula Gupta, Journal of Computational and Theoretical Nanoscience (JCTN). (Accepted for Publication)

  10. "An Accurate Charge-Control- Based Approach for Noise Performance Assessment of a Symmetric Tied-Gate INAlAs/INGaAs DG HEMT" Monika Bhattacharya, Jyotika Jogi, R.S Gupta and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 59 , no. 6, pp. 1644 – 1652, June 2012

  11. "Analog and Digital Performance Assessment of Empty Space in Double Gate (ESDG) MOSFET: A Novel Device Architecture" Vandana Kumari, Manoj Saxena, R.S. Gupta, and Mridula Gupta, Journal of computational and theoretical nanoscience (JCTN). (In press)

  12. "Temperature Dependent Drain Current Model for Gate stack Insulated Shallow Extension Silicon on Nothing (ISESON)MOSFET for wide operating temperature range" Vandana Kumari, Manoj Saxena, R.S. Gupta, and Mridula Gupta, Microelectronics Reliability. Vol. 52, no. 6, pp. 974–983, June 2012.

  13. "Immunity against Temperature Variability and Bias point Invariabilityin Double Gate Tunnel Field Effect Transistor" Rakhi Narang, Manoj Saxena, R.S. Gupta, and Mridula Gupta, Microelectronics Reliability. Vol. 52, pp. 1617–1620, 2012.

  14. "Effect of Localised Charges on Nanoscale Cylindrical Surrounding Gate MOSFET: Analog Performance and Linearity Analysis" Rajni Gautam, Manoj Saxena, R.S.Gupta and Mridula Gupta, Microelectronics Reliability, vol. 52, no.6, pp. 989-994, June 2012.

  15. "Gate-Geometric Recessed Nano-scale In0.52Al0.48As-In0.53Ga0.47As Double–Gate HEMT for High Breakdown" Servin Rathi, Mridula Gupta and R. S. Gupta, IEEE Transaction on Device and Material Reliability Vol. 12, No. 1, pp.139-145, 2012.

  16. "Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications" Vandana Kumari, Manoj Saxena, R.S. Gupta, and Mridula Gupta, Microelectronics Reliability. Vol. 52, pp. 1610-1612, 2012.

  17. "Two Dimensional Analytical Subthreshold Model of Nanoscale Cylindrical Surrounding Gate MOSFET Including Impact of Localised Charges", Rajni Gautam, Manoj Saxena, R.S.Gupta and Mridula Gupta, Journal of computational and theoretical nanoscience, Vol.9, No.4, p.602-610. (April) 2012.

  18. "Dielectric Modulated Tunnel Field Effect Transistor – A Bio molecule Sensor" Rakhi Narang, Manoj Saxena, R.S. Gupta, and Mridula Gupta, IEEE Electron Device Letters, vol. 33, no. 2, pp. 266-268, Feb 2012.

  19. "An Analytical Drain Current Model for Dual Material Engineered Cylindrical/Surrounded Gate MOSFET", Pujarini Ghosh, Subhasis Haldar, R.S. Gupta, and Mridula Gupta, Microelectronics Journal Vol. 43, No. 1, pp.17-24, 2012.

  20. "Linearity and Analog Performance Analysis of Double Gate Tunnel Fet: Effect of Temperature and Gate Stack", Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International journal of VLSI design & Communication Systems ( VLSICS).,Vol. 2, No. 3, P.185-200, (September), 2011.

  21. "Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET", Rajni Gautam, Manoj Saxena, R.S. Gupta , and Mridula Gupta, AIRCC journal (International journal of VLSI design & Communication Systems VLSICS ), Vol. 1, No. 3, P. 225-241, (September), 2011.

  22. "AC Analysis of nanoscale GME-TRC MOSFET for Microwave and RF Applications", Priyanka Malik, R.S.Gupta, Rishu Chaujar and Mridula Gupta. Microelectronic Reliability, Vol. 52, no. 1, pp. 151-158, (January) 2012.

  23. "Linearity-Distortion analysis of GME-TRC MOSFET for High Perfromance and Wireless Applications", Priyanka Malik, R.S.Gupta, Rishu Chaujar and Mridula Gupta, Journal of Semiconductor Technology and Science, P. 152-174, (July) 2011.

  24. "TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET", Rupendra Sharma, Mridula Gupta and R.S Gupta, IEEE Trans. Electron Devices. Vol. 58, No. 9, P. 2936-2943, (September), 2011.

  25. "Scattering parameter based Modeling and Simulation of symmetric tied-gate InAlAs/InGaAs DG-HEMT for millimeter-wave applications", Monika Bhattacharya, Jyotika Jogi, R.S Gupta and Mridula Gupta. Solid State Electronics, Vol.63, No.1, P.149-153, (September) 2011.

  26. "Improved Linearity Performance of AlGaN/GaN MISHFET over Conventional HFETs: An Optimization Study for Wireless Infrastructure Applications", Ruchika Aggarwal, Anju Agrawal, R.S Gupta. and Mridula Gupta. Superlattice and Microstructures. Vol.50, No. 1, P.1-13, (July) 2011.

  27. "Device linearity and intermodulation distortion comparison of Dual Material Gate and conventional AlGaN/GaN High Electron Mobility Transistor", Sona P Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R.S. Gupta. Microelectronics Reliability. Vol. 51, No.3, P. 587-596, (March) 2011.

  28. "Physics Based Threshold voltage analysis of Gate Material Engineered Trapezoidal Recessed Channel (GME TRC) Nanoscale MOSFET and its Multilayered gate architecture", Priyanka Malik, Rishu Chaujar, Mridula Gupta and R.S Gupta. International Journal of Microwave and Optical Technology, Vol.5, No.6, P.361-368, (Nov) 2010.

  29. "An analytical charge-based drain current model for nanoscale In0.52Al0.48As-In0.53Ga0.47 As separated double-gate HEMT", Servin Rathi, Jyotika Jogi, R.S. Gupta and Mridula Gupta, Semiconductor Science and Technology, Vol. 25, No.11, P. 115003-115009, (Oct) 2010.

  30. "Microwave performance enhancement in Double and Single Gate HEMT with channel thickness variation". Ritesh Gupta, Servin Rathi, Mridula Gupta and R S Gupta, Superlattice and Microstructures, Vol. 47, No. 6, P. 779-794, (June) 2010.

  31. "Analytical modeling of Channel noise for Gate Material Engineered Surrounded/Cylindrical Gate (SGT/CGT) MOSFET", Pujarini Ghosh, Rishu Chaujar, Subhasis Haldar, R.S Gupta and Mridula Gupta, World Academy of Science, Engineering and Technology Journal No.64 (April), 2010.

  32. "Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications", Ritesh Gupta, Ravneet Kaur, Sandeep Kr Aggarwal, Mridula Gupta, and R. S. Gupta, Journal of Semiconductor Technology and Science, Vol.10, No.1, 66-77, (March), 2010.

  33. "Gate Material Engineered-Trapezoidal Recessed Channel MOSFET (GME-TRC) for Ultra Large Scale Integration (ULSI)" Priyanka Malik, Sona P. Kumar, Rishu Chaujar, Mridula Gupta & R.S. Gupta, Microwave and Optical Technology Letters, Vol. 53, No. 3, P.694-698, 2010.

  34. "TCAD Performance Investigation of a Novel MOSFET Architecture of Dual Material Gate Insulated Shallow Extension Silicon On Nothing (DMG ISE SON) MOSFET for ULSI era" Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Microwave and Optical Technology Letters, Vol. 53, No. 3, P.746-750, 2010.

  35. "Design considerations and impact of technological parametric variations on RF/microwave performance of GEWE-RC MOSFET" Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Microwave and Optical Technology Letters, Vol. 53, No. 3, P.652-657, 2010.

  36. "Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs-InGaAs symmetric double-gate HEMT", Servin Rathi, Jyotika Jogi, Mridula Gupta, R.S. Gupta, Microelectronics Reliability, Vol. 49, pp. 1508-1514, 2009.

  37. "TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multi-layered gate architecture: Part II: Analog and large signal performance evaluation", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Superlattices and Microstructeres, Vol. 46, No. 4, Pp. 645-655, October 2009.

  38. "Dual-material double-gate SOI n-MOSFET: Gate misalignment analysis", Rupendra Kumar Sharma, Ritesh Gupta, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 56, No. 6, 1284–1291, 2009.

  39. "Dynamic Performance of Graded Channel DG FD SOI n-MOSFETs for Minimizing the Gate Misalignment Effect", Rupendra Kumar Sharma, Mridula Gupta and R.S. Gupta, Microelectronics Reliability, Vol. 49, No. 6, pp. 592-599, June 2009.

  40. "Investigation of Multi-Layered-Gate Electode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 22, No. 3, Pp. 259-278, May/June 2009.

  41. "T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers" Ritesh Gupta, Servin Rathi, Ravneet Kaur, Mridula Gupta, R.S. Gupta, Superlattices and Microstructures, Vol. 45, No. 3, Pp. 105-116, 2009.

  42. "Two-Dimensional Analytical Subthreshold Model of Graded Channel DG FD SOI n-MOSFET with Gate Misalignment Effect", Rupendra Kumar Sharma, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol. 45, Pp. 91-104, 2009.

  43. "Two Dimensional Simulation and Analytical Modeling of a Novel ISE MOSFET with Gate Stack Configuration", Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Microelectronic Engineering, Vol. 86, Pp. 2005-2014, 2009.

  44. "Two-dimensional threshold voltage model and design considerations for gate electrode workfunction engineered recessed channel (GEWE-RC) nanoscale MOSFET: part 1", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Semiconductor Science and Technology, Vol. 23, 045006 (10pp), 2008.

  45. "Modeling and Analysis of Fully Strained and Partially Relaxed Lattice Mismatched AlGaN/GaN HEMT for High Temperature Applications", Parvesh Gangwani, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol. 44, No. 6, Pp. 781-793, Dec. 2008.

  46. "Gate Dielectric Engineering of Quarter Sub Micron AlGaN/GaN MISHFET: A New Device Architecture for Improved Transconductance and High Cut-off Frequency", Ruchika Aggarwal, Anju Agrawal, Mridula Gupta and R.S. Gupta, Solid State Electronics, Vol. 52, Pp. 1610-1614, 2008.

  47. "On-State and RF Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic and Switching Applications" Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Semiconductor Science and Technology, Vol. 23, 095009 (8pp), 2008.

  48. "TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation" Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 10, Pp. 2602-2613, 2008.

  49. "Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length LDUMGAC MOSFET for RFIC Design" Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol. 44, Pp.143-152, 2008.

  50. "Graded Channel Architecture: the Solution for Misaligned DG FD SOI n-MOSFETs", Rupendra Kumar Sharma, Ritesh Gupta, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol. 23, No. 7, Pp., 075041, 2008.

  51. "Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN HEMT" Sona P. Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol. 44, No. Pp. 37-53, July 2008.

  52. "Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale MOSFET", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Semiconductor Science and Technology, Vol. 23, No. 4, (10pp), April 2008.

  53. "Dual Material Double Layer Gate Stack SON MOSFET: A Novel Architecture for enhanced analog performance – Part II Impact of Gate Dielectric Material Engineering", Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 1, Pp. 382-387, 2008.

  54. "Dual Material Double Layer Gate Stack SON MOSFET: A Novel Architecture for enhanced analog performance – Part I Impact of Gate Metal Workfunction Engineering", Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 1, Pp. 372-381, 2008.

  55. "Laterally amalgamated Dual Material Gate Concave (L-DUMGAC) MOSFET for ULSI", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Microelectronic Engineering, Vol. 85, Pp. 566 – 576, March 2008.

  56. "Analytical Performance Evaluation of AlGaN/GaN Metal Insulator Semiconductor Heterostructure Field Effect Transistor (MISHFET) and its Comparison with Conventional HFETs for High Power Microwave Applications" Ruchika Aggarwal, Anju Agrawal, Mridula Gupta and R.S. Gupta, Microwave and Optical Technology Letters, Vol. 50, No. 2, P.331 – 338, (February) 2008.

  57. "Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency", version 3 Amit Sehgal, Tina Mangla, Mridula Gupta, R. S. Gupta, Thin Solid Films, Vol. No. 516, Pp. 2162-2170, 2008.

  58. "Temperature dependent analytical model of sub-micron GaN MESFETs for microwave frequency applications" Sneha Kabra, Harsupreet Kaur, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Solid State Electronics, Vol. 52, Pp. 25-30, 2008.

  59. "Poly-crystalline silicon thin film transistor: a two-dimensional threshold voltage analysis using green's function approach", Amit Sehgal, Tina Mangla, Mridula Gupta and R.S. Gupta, Journal of Semiconductor Technology and Science, Vol. 7, No. 4, Pp. 287 – 298, 2007.

  60. "Threshold Voltage Model For Small Geometry AlGaN/GaN HEMTs Based on Analytical Solution of 3-D Poisson's Equation" Sona P. Kumar, Anju Aggarwal, Rishu Chaujar, Sneha Kabra, Mridula Gupta and R.S. Gupta, Microelectronics Journal, Vol. 38, Pp. 1013-1020, 2007.

  61. "A Semi-Empirical Model for Admittance and Scattering Parameters of GaN MESFET for microwave circuit applications" Sneha Kabra, Harsupreet Kaur, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Microwave and Optical Technology Letters, Vol. 49, No. 10, Pp.2446-2450, 2007.

  62. "Short channel analytical model for high electron mobility transistor to obtain higher cut-off frequency maintaining the reliability of the device", Ritesh Gupta, Sandeep Kr. Aggarwal, Mridula Gupta and R.S. Gupta, Journal of Semiconductor Technology and Science, Vol. 7, No. 2, P. 120-131, June 2007.

  63. "Unified model for physics based modeling of a new device architecture: Triple Material Gate Oxide Stack Epitaxial Channel Profile (TRIMGAS Epi) MOSFET" Kirti Goel, Manoj Saxena, Mridula Gupta and R.S. Gupta, Semiconductor Science and Technology, Vol. 22, No. 4, Pp.435-446 , 2007.

  64. "Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability" Harsupreet Kaur, Sneha Kabra, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Solid-State Electronics, Vol. 51, 398-404, (March) 2007.

  65. "Polarization dependent analysis of AlGaN/GaN HEMT for high power applications" Parvesh, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Solid State Electronics, Vol. 51, Pp. 108-113, 2007.